1. Field
The present invention relates to time-to-digital converter circuits and, more particularly, to time-to-digital converter circuits with resistance to metastability errors.
2. Background
Systems such as delay-locked loops (DLL) and phase-locked loops (PLLs), in particular, all-digital phase locked loops (ADPLL) may use time-to-digital converter (TDC) circuits to measure the time between events (signal transitions). TDC circuits may also be used to measure circuit delays, for example, in a dynamic voltage scaling system. If a TDC circuit produces erroneous values, operation of the system using the TDC circuit will be impaired.
TDC circuits measure times between signal transitions that are asynchronous. The asynchronous operation can cause measurement errors in a TDC circuit for some signal timings. The error can be large, for example, on the order of one hundred times the resolution of the output. Such errors can greatly impair operation of a system using the TDC circuit.